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| Ordering number : EN*5611A CMOS IC LC378100QM, QT 8 MEG (1048576 words x 8 bits) Mask ROM Internal Clocked Silicon Gate Preliminary Overview The LC378100QM and LC378100QT are 1,048,576-word x 8-bit organization (8,388,608-bit) mask programmable read only memories. They feature a wide operating voltage range (2.6 to 5.5 V), a 100-ns access time (tCA) at VCC = 4.5 to 5.5 V, and a 200-ns access time at VCC = 2.6 to 3.3 V. Thus these LSIs can be used in a wide range of systems, from 5-V systems that require high-speed access to 3-V systems that use batteries. Package Dimensions unit: mm 3205-SOP32 [LC374100QM] Features * 1048576 words x 8 bits organization * Supply voltage range: 2.6 to 5.5 * Fast access time(tAA): 120 ns (max.) VCC = 4.5 to 5.5 V (tCA): 100 ns (max.) VCC = 4.5 to 5.5 V 200 ns (max.) VCC = 2.6 to 5.5 V * Operating current 55 mA (max.) * Standby current 30 A (max.) * Full static operation (internal clocked type) * 3 state outputs * JEDEC standard pin configuration * Package type LC378100QM: SOP32 (525 mil) LC378100QT: TSOP32 (8 mm x 20 mm) SANYO: SOP32 unit: mm 3224-TSOP32 [LC374100QT] SANYO: TSOP32 (type-I) SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 53098HA (OT) No. 5611-1/4 LC378100QM, QT Pin Assignments Pin Functions A0 to A16 D0 to D7 CE OE VCC VSS Address input Data output Chip enable input Output enable input Power supply Ground Block Diagram Truth Table CE H L L OE X H L Output Current drain High-impedance Standby mode High-impedance Operating mode DOUT Operating mode X: H or L level should be offered. No. 5611-2/4 LC378100QM, QT Specifications Absolute Maximum Ratings *1 Parameter Supply voltage Supply input voltage Supply output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC VIN VOUT Pd max Topr Tstg Ta = 25C; Reference values for the SANYO DIP package Conditions Ratings -0.3 to +7.0 -0.3*2 to VCC + 0.3 -0.3 to VCC + 0.3 1.0 -10 to +70 -55 to +125 Unit V V V W C C Note: 1. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to Recommended Operating Conditions. 2. VIN (min) = -3.0 V (pulse width 30 ns) Input/Output Capacitance* at Ta = 25C, f = 1.0 MHz Parameter Input capacitance Output capacitance Symbol CIN COUT Conditions VIN = 0 V; Reference values for the SANYO DIP package VOUT = 0 V; Reference values for the SANYO DIP package Ratings min typ max 8 10 Unit pF pF Note: * This parameter is periodically sampled and not 100% tested. DC Recommended Operating Ranges at Ta = -10 to +70C, VCC = 2.6 to 5.5 V Parameter Supply voltage Input high level voltage Input low level voltage Symbol VCC VIH VIL Conditions Ratings min 2.6 2.2 -0.3 typ 5.0 max 5.5 VCC + 0.3 +0.6 Unit V V V DC Electrical Characteristics at Ta = -10 to +70C, VCC = 2.6 to 5.5 V Parameter Symbol ICCA1 ICCA2 ICCS1 ICCS2 ILI ILO VOH VOL Conditions CE = 0.2 V, VI = VCC - 0.2 V/0.2 V CE = VIL, IO = 0 mA, VI = VIH/VIL, f = 10 MHz CE = VCC - 0.2 V CE = VIH VIN = 0 to VCC CE or OE = VIH, VOUT = 0 to VCC IOH = -0.5 mA IOL = 0.5 mA 0.8 VCC 0.2 Ratings min typ max 30 55 30 (1.0) 1.0 (300) 1.0 1.0 Unit mA mA A mA(A) A A V V Operating supply current Standby supply current Input leakage current Output leakage current Output high level voltage Output low level voltage Note: * Guaranteed at Ta = 25C AC Characteristics at Ta = -10 to +70C, VCC = 2.6 to 5.5 V Parameter Cycle time Address access time CE access time OE access time Output hold time Output disable time*1 Symbol tCYC tAA tCA tOA tOH tOD*1 20 100 Conditions Ratings min 200 (120) 200 (120) 200 (100) 80 (40) typ max Unit ns ns ns ns ns ns Note: 1. tOD is measured from the earlier edge of the CE or OE's going high impedance. This parameter is periodically sampled and not 100% tested. 2. Guaranteed at VCC = 4.5 to 5.5 V No. 5611-3/4 LC378100QM, QT AC Test Conditions Input pulse levels Input rise/fall time Input timing level Output timing level Output load 0.4 to 2.8 V 5 ns 1.5 V 1.5 V See Figure 1 Figure 1 Output Load Timing Chart System Design Notes These LSIs adopt the ATD technique, in which operation starts when a change in either the CE or address inputs is detected. This means that the output data immediately after power is applied is invalid. When using these LSIs as program memory for Z80 and similar microprocessors, applications must take into account the fact that valid data will not be output after power is first applied unless the value of either the CE or at least one of the address lines is changed after the power supply has stabilized. Another point due to the use of the ATD technique is that these LSIs are sensitive to input noise. Do not apply voltages outside the allowable DC input levels for extended periods and do not apply input voltages with large noise components. s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 1998. Specifications and information herein are subject to change without notice. PS No. 5611-4/4 |
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